Semiconductor Integrated Circuit Device and Method for Producing the Same

ABSTRACT

A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Continuation of U.S. patent application Ser. No. 14/661,734,filed Mar. 18, 2015, now U.S. Pat. No. ______, which claims priority toJapanese Patent Application No. 2014-056185 filed on Mar. 19, 2014. Thecontents of the aforementioned application are incorporated by referencein their entirety.

BACKGROUND

The present invention relates to a semiconductor integrated circuitdevice, and a method for producing the device, and relates to, forexample, a DRAM having a capacitive element (capacitor) of a metalinsulator metal (MIM) structure, or an embedded dynamic random accessmemory (eDRAM) on which a DRAM having a capacitor of an MIM structure,and a logic circuit are consolidated.

For example, a DRAM in an eDRAM has, for example, plural word linesextended in a first direction of a main surface of a semiconductorsubstrate, plural bit lines extended to a second direction crossing thefirst direction, and plural DRAM cells coupled electrically to the wordlines and the bit lines and each arranged at a site where one of theword lines crosses one of the bit lines.

The DRAM cells each include a single selective metal insulator fieldeffect transistor (MISFET), and a single capacitive element coupledthereto in series. The selective MISFET has a gate electrode formed tobe integrated with one of the word lines, and semiconductor regionsincluding a source and a drain, respectively. One of the source and thedrain is electrically coupled to one of the bit lines; and the other, tothe capacitive element. The capacitive element includes a lowerelectrode coupled to one of the source and the drain of the selectiveMISFET, an upper electrode opposed to the lower electrode, and acapacitive insulator film sandwiched between the lower and upperelectrodes.

The logic circuit includes a p-channel type MISFET (pMISFET), ann-channel type MISFET (nMISFET), and an interconnection through whichthe p-channel type MISFET (pMISFET) is electrically coupled to then-channel type MISFET (nMISFET). The pMISFET has a gate electrode, and apair of p-type semiconductor regions in which a source and a drain areconfigured, respectively. The nMISFET has a gate electrode, and a pairof n-type semiconductor regions in which a source and a drain areconfigured, respectively. The interconnection is made of a conductorfilm such as an aluminum film or cupper film, and is a multilayeredinterconnection layer having five, six or more layers. Over thecapacitive element, many interconnection layers are laid.

Patent Literatures 1 and 2 listed below each disclose, for example, acapacitive element including a titanium nitride (TiN) film as a lowerelectrode, a zirconium oxide (ZrO₂) film as a capacitive insulator film,and a laminated film of a titanium nitride (TiN) film and a tungsten (W)film as an upper electrode.

CITATION LIST Patent Literatures

Patent Literature 1: Japanese Unexamined Patent Application Publication(Japanese Patent Application Laid-Open) No. 2002-373945

Patent Literature 2: Japanese Unexamined Patent Application PublicationNo. 2005-243921

The inventors have investigated, for example, an eDRAM having acapacitive element of an MIM structure including a titanium nitride(TiN) film as a lower electrode, a zirconium oxide (ZrO₂) film as acapacitive insulator film, and a laminated film of a titanium nitride(TiN) film and a tungsten (W) film as an upper electrode.

While the shrinkage of eDRAMs has been advanced, a lower electrode, acapacitive insulator film and an upper electrode configured in theircapacitive element have been made small in film thickness, whereby areduction in the area of the capacitive element as viewed in plan hasbeen attained. However, as the capacitive insulator film and the upperelectrode have been made smaller in film thickness, a leakage in thecapacitive insulator film, that is, a leakage current between the upperelectrode and the lower electrode has been increasing to deteriorate theeDRAMs in electric properties. The inventors have come to recognize thisproblem.

SUMMARY

The inventors' investigations have made the following clear: impurities,such as fluorine (F), contained in a tungsten (W) film or an interlayerdielectric of any eDRAM are caused to diffuse into a capacitiveinsulator film thereof by a thermal load in, for example, the step offorming the interlayer dielectric after the tungsten (W) film is formed;as a result, a leakage is generated in the capacitive insulator film, sothat the capacitive element is deteriorated in electric properties.

Accordingly, techniques for improving the capacitive element in electricproperties have been desired.

Other objects and novel features will be made evident from thedescription of the present specification, and the attached drawings.

According to an aspect, provided is a capacitive element that may beconfigured in a DRAM cell of an eDRAM, and that has a lower electrode, acapacitive insulator film formed over the lower electrode, and an upperelectrode formed over the capacitive insulator film. The upper electrodehas a structure in which from the capacitive insulator film side of thiselectrode, a first upper electrode, a second upper electrode and a thirdupper electrode are stacked in turn. The third upper electrode includesa tungsten film that may contain an impurity. Between the first andthird upper electrodes, the second upper electrode is interposed whichis a barrier film preventing the possible impurity contained in thethird upper electrode from diffusing into the capacitive insulator film.

According to the present aspect, a capacitive element can be improved inelectric properties.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram of a DRAM cell array in asemiconductor integrated circuit device of First embodiment.

FIG. 2 is a sectional view of a main portion of a DRAM region and alogic circuit region of the semiconductor integrated circuit device ofthe First embodiment.

FIG. 3 is a sectional view of a main portion of a workpiece of thesemiconductor integrated circuit device of the First embodiment, theview demonstrating a method for producing this device.

FIG. 4 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 3 in this method.

FIG. 5 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 4.

FIG. 6 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 5.

FIG. 7 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 6.

FIG. 8 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 7.

FIG. 9 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 8.

FIG. 10 is a sectional view which is equivalent to FIG. 3 butdemonstrates a step after the step illustrated in FIG. 9.

FIG. 11 is a graph showing a relationship between the film density andthe film thickness of a barrier film.

FIG. 12 is a graph showing a relationship between the leakage current ofeach capacitive element species and a cumulative probabilitydistribution of samples of the species.

FIG. 13 is a graph showing a concentration distribution of fluorine inthe depth direction of each sample of a first upper electrode.

FIG. 14 is a graph showing a relationship between the depth of fluorinediffusing into each bather film species and the concentration offluorine therein.

DETAILED DESCRIPTION

Hereinafter, embodiments will be described in detail with reference tothe drawings. In all the drawings referred to for describing theembodiments, the same reference sign or number is attached to membershaving the same function. A repeated description thereon is omitted.Moreover, in the embodiments described hereinafter, any repeateddescription on the same or similar regions or portions is not inprinciple made unless especially required.

Even when any one of the drawings referred to for the description on theembodiments is a sectional view, a hatching therein may be omitted tomake the drawing easy to view. Even when any one of the drawings is aplan view, a hatching may be applied thereto to make the drawing easy toview.

In the embodiments, the “film density” of any film denotes the volumedensity of the film, and the numerical value thereof is a value obtainedby X-ray reflection (XRR).

First Embodiment

A semiconductor integrated circuit device of each of the presentembodiment and an embodiment that will be described later has an eDRAM.Such an eDRAM has a DRAM region DR and a logic circuit region LGC. TheDRAM region DR has a DRAM cell array in which DRAM cells are arranged ina matrix form. Each of the DRAM cells is configured to have a singlen-channel type selective MISFET, and a single capacitive element coupledin series to this MISFET. Hereinafter, any selective MISFET will bedescribed about one of an n-channel type. However, a p-channel typeselective MISFET may be used. In the logic circuit region LGC, pluraln-channel type MISFETs and p-channel type MISFETs are arranged. However,in the present embodiment, the n-channel type MISFETs are given as anexample, and only this example will be described.

FIG. 1 is a view illustrating an equivalent circuit diagram of a DRAMcell array in a DRAM region DR in the present embodiment. In the DRAMcell array, plural DRAM cells are arranged in a matrix form, and theDRAM cells are each configured to have an n-channel type selectiveMISFET (TR1), and a capacitive element CON having an MIM structure andcoupled in series to this MISFET. The DRAM cell array has plural wordlines WL extended to a first second, and plural bit lines BL extended ina second direction orthogonal to the first direction. The DRAM cells areeach arranged at a site where one of the word lines WL crosses one ofthe bit lines BL. The word line WL and the bit line BL are electricallycoupled to each other.

FIG. 2 is a sectional view of a main portion of the DRAM region DR and alogic circuit region LGC in the present embodiment. In the DRAM regionDR, two of the DRAM cells are illustrated, and in the logic circuitregion LGC, one n-channel type logic MISFET (TR2) is illustrated. Thelogic MISFET (TR2), and selective MISFETs (TR1) configured in therespective DRAM cells are formed in a main surface of a semiconductorsubstrate SB made of, for example, p-type silicon. The semiconductorsubstrate SB may be a silicon-on-insulator (SOI) substrate in which asupporting substrate, an insulator film, and a p-type silicon substrateare stacked over each other in this order. The semiconductor substrateSB may be an n-type silicon semiconductor substrate SB, or an SOIsubstrate in which a supporting substrate, an insulator film, and ann-type silicon substrate are stacked over each other in this order. Thesemiconductor substrate SB may be a germanium substrate. In the mainsurface (front surface) of the semiconductor substrate SB, anelectrically-insulating element isolation film ST1 is formed to surrounda first active region ACT1 and a second active region ACT2. The elementisolation film ST1 is, for example, a silicon oxide film.

In the first active region ACT1 in the DRAM region DR, the selectiveMISFETs (TR1), the number of which is two, are formed. The selectiveMISFETs (TR1) each have a gate electrode G1, a source region SR1 and adrain region DR1. The gate electrode G1 is formed over the main surfaceof the semiconductor substrate SB to interpose a gate insulator film GI1therebetween. The source region SR1 and the drain region DR1 are formedin the main surface of the semiconductor substrate SB and at both sideof the gate electrode G1. A side wall film SW1 that is an insulator filmis formed on the side wall of the gate electrode G1. A conductivesilicide film SIL is formed on the main surface (front surface) of thegate electrode G1 and the respective main surfaces (front surfaces) ofthe source region SR1 and the drain region DR1.

The logic MISFET (TR2) in the logic circuit region LGC is formed insidethe second active region ACT2, and has a gate electrode G2, a sourceregion SR2 and a drain region DR2. The gate electrode G2 is formed overthe main surface of the semiconductor substrate SB to interpose a gateinsulator film G12 therebetween. The source region SR2 and the drainregion DR2 are formed in the main surface of the semiconductor substrateSB and at both side of the gate electrode G2. A side wall film SW2 thatis an insulator film is formed on the side wall of the gate electrodeG2. The conductive silicide film SIL is formed on the main surface(front surface) of the gate electrode G2 and the respective mainsurfaces (front surfaces) of the source region SR2 and the drain regionDR2.

The gate electrode G1 and the gate electrode G2 are each made of apolycrystal silicon film (polysilicon film). The source region SR1, thedrain region DR1, the source region SR2, and the drain region DR2 areeach made of an n-type semiconductor region. The side wall films SW1 andSW2 are each, for example, a silicon oxide film, a silicon nitride film,or a laminated film of a silicon oxide film and a silicon nitride film.The silicide film Sit, may be a nickel silicide film, or aplatinum-added nickel silicide film (platinum-contained nickel silicidefilm).

The gate electrode G1 (i.e., each of the gate electrodes G1) and thegate electrode G2 may each be made into a metal gate structure. In thiscase, the gate electrodes may each have a W/TiN laminated structure, andthe gate insulator films GI1 and GI2 may each be a laminated film ofSiON or HfAlO_(x), and SiO₂. The metal gate structure may be formed in aknown gate-first manner or a gate-last manner. The selective MISFETs(TR1) and the logic MISFET (TR2) may be formed to have an embedded gatestructure in which the gate insulator films GI1 and G12 and the gateelectrodes G1 and G2 are embedded in trenches made in the semiconductorsubstrate SB.

In the DRAM region DR and the logic circuit region LGC, an interlayerdielectric INS1 that is an insulator film is formed on the semiconductorsubstrate SB to cover the selective MISFETs (TR1) and the logic MISFET(TR2). The interlayer dielectric INS1 covers the respective mainsurfaces (upper surfaces) of the gate electrodes G1 and the gateelectrodes G2. Even when a bit line BL extended in the second directionoverlaps with the gate electrodes G1 extended in the first directionwhen viewed in plan, the bit line BL does not short-circuit the gateelectrodes G1. The interlayer dielectric INS1 may be a silicon oxidefilm or a silicon nitride film, or may have a laminated structure of asilicon oxide film on a silicon nitride film. In the DRAM region DR andthe logic circuit region LGC, plural contact holes CH1 are made in theinterlayer dielectric INS1 to penetrate the interlayer dielectric INS1.Plural plug electrodes that are each made of a conductor film are formedinside the contact holes CH1, respectively. The plug electrodes eachhave a laminated structure of the following two: a thin bather conductorfilm (such as a titanium nitride (TiN) film, a titanium (Ti) film or alaminated film of the two) functioning as a bather metal; and a mainconductor film (such as a tungsten film) that is larger in filmthickness than the bather conductor film. The plug electrodes penetratethe interlayer dielectric INS1 in the film thickness direction thereof,and the respective upper surfaces of the plug electrodes are exposed tothe front surface of the interlayer dielectric INS1. The plug electrodesinclude a source electrode PLGS connected to the source region SR1 ofthe selective MISFETs (TR1), drain plug electrodes PLGD connected to therespective drain regions DR1 of the selective MISFETs (TR1), and plugelectrodes PLG1 connected to the source region SR2 or the drain regionDR2 of the logic MISFETs (TR2).

An interlayer dielectric INS2 that is an insulator film is formed on theinterlayer dielectric INS1. The interlayer dielectric INS2 is an siliconoxide film. Plural interconnection trenches CH2 a and plural contactholes CH2 b are made in the interlayer dielectric INS2. The bit line BLis formed in one of the contact holes CH2 a, which is an interconnectiontrench CH2 a in the DRAM region DR. An interconnection M1 is formed inthe other, which is an interconnection trench CH2 a in the logic circuitregion LGC. In some of the contact holes CH2 b, which are contact holesCH2 b in the DRAM region DR, capacitive plug electrodes PLGC are formed.In the other contact hole CH2 b, which is a contact hole CH2 b in thelogic circuit region LGC, a plug electrode PLG2 is formed. Thecapacitive plug electrodes PLGC are each stacked on one of the drainplug electrodes PLGD to be electrically coupled, through the drain plugelectrode PLGD, to one of the respective drain regions DR1 of theselective MISFETs (TR1). The bit line BL is formed to cover the uppersurface of the source plug electrode PLGS to be electrically coupled,through the source plug electrode PLGS, to the source region SR1 of theselective MISFETs (TR1). The plug electrode PLG2 in the logic circuitregion LGC is stacked on one of the plug electrodes PLG1 to beelectrically coupled, through the plug electrode PLG1, to the drainregion DR2 of the logic MISFET (TR2). The interconnection M1 is formedto cover the upper surface of the other plug electrode PLG1 to beelectrically coupled, through the plug electrode PLG1, to the sourceregion SR2 of the logic MISFET (TR2).

The capacitive plug electrodes PLGC, the bit line BL, the plug electrodePLG2, and the interconnection M1 are formed to have a laminatedstructure of the following two: a thin bather conductor film (such as atitanium nitride (TiN) film, a titanium (Ti) film or a laminated film ofthe two) functioning as a bather metal; and a main conductor film (suchas a tungsten film) that is larger in film thickness than the barrierconductor film.

A stopper film STP1 that is an insulator film is formed on therespective upper surfaces of the capacitive plug electrodes PLGC, theplug electrode PLG2, the bit line BL and the interconnection M1. Thestopper film STP1 may be a silicon nitride film. In the DRAM region DR,plural capacitive contact holes CCH, which are holes penetrating thestopper film STP1, are made in the stopper Film STP1 to be exposed tothe respective upper surfaces of the capacitive plug electrodes PLGC.The capacitive contact holes CCH are each circular when viewed in plan.The diameter thereof is set to not more than the diameter of the uppersurface of each of the capacitive plug electrodes PLGC to prevent thecapacitive contact hole CCH from overlapping with the bit line BL.

An interlayer dielectric INS3 is formed on the stopper film STP1. Theinterlayer dielectric INS3 is, for example, an insulator film such as asilicon oxide film. The film thickness thereof is from 550 to 650 nm. Inthe DRAM region DR, plural capacitor-forming trenches CGV penetratingthe interlayer dielectric INS3 are made. The capacitor-forming trenchesCGV are each configured by the side wall (side surface) of theinterlayer dielectric INS3 and the main surface of the stopper filmSTP1. Hereinafter, when wordings such as the wordings “the bottomsurface of each of the capacitor-forming trenches CGV” and “the sidewall (side surface) thereof” are used, the bottom surface denotes themain surface of the stopper film STP1; and the side wall (side surface)thereof, the side wall (side surface) of the interlayer dielectric INS3.The capacitor-forming trenches CGV each have an elliptic shape whenviewed in plan. The minor axis thereof is from 180 to 200 nm in length,and the major axis thereof is from 220 to 260 nm in length. The aspectratio of each of the capacitor-forming trenches CGV (the ratio of thedepth of the trench to the minimum width of the opening of the trench)is 3 or more.

Along/on the respective bottom surfaces and side walls of thecapacitor-forming trenches CGV, lower electrodes EL of the capacitiveelements CON are formed. Each of the lower electrodes EL is electricallycoupled to one of the capacitive plug electrodes PLGC. As describedabove, the bottoms of the capacitor-forming trenches CGV denote the mainsurface of the stopper film STP1; and the side wall (side surface)thereof, the side wall (side surface) of the interlayer dielectric INS3.For the lower electrode EL, a metal or metal-element-containing materialis usable, examples thereof including titanium nitride (TiN), titanium(Ti), tungsten (W), tungsten nitride (WN), platinum, and ruthenium (Ru).The film thickness thereof is from 3 to 40 nm. The lower electrode ELcan be formed by a physical vapor deposition (PVD) method, a chemicalvapor deposition (CVD) method (in particular, a metal organic chemicalvapor deposition (MOCVD) method), or an atomic layer deposition (ALD)method. The length of the minor axis of each of the capacitor-formingtrenches CGV, which is elliptic when viewed in plan, is sufficientlylarger than twice the film thickness of the lower electrode EL; thus,the capacitor-forming trench CGV is not embedded with any one of thelower electrodes EL. Each of the lower electrodes EL is formed into asmall and even thickness along/on the bottom surface and the side wallof one of the capacitor-forming trenches CGV. The lower electrode EL isterminated inside the capacitor-forming trench CGV not to be extended tothe upper surface (main surface) of the interlayer dielectric INS3positioned outside the capacitor-forming trench CGV. About the lowerelectrode EL, a surface thereof that is near to a capacitive insulatorfilm CINS, which will be described later, is called the upper surfacethereof; a surface thereof that is far therefrom, the lower surface.

The above has described an example in which each of the lower electrodesEL directly contacts one of the capacitive plug electrodes PLGC.However, for example, a plug electrode (not illustrated) that is aconductor film, such as a titanium nitride (TiN) film, a titanium (Ti)film or a tungsten (W) film, may be interposed between the lowerelectrode EL and the capacitive plug electrode PLGC since it isimportant that the two members EL and PLGC are electrically coupled toeach other.

A capacitive insulator film CINS is formed to cover the respective uppersurfaces of the lower electrodes EL. An upper electrode EU is formed tocover the upper surface of the capacitive insulator film CINS. About thecapacitive insulator film CINS, the surface thereof that is near to thelower electrodes EL is called the lower surface thereof; and the surfacethereof that is far therefrom, the upper surface thereof. The capacitiveinsulator film CINS and the upper electrode EL are formed commonly orsingly for plural capacitive elements CON (including the illustratedelements CON). In the DRAM region DR, the capacitive insulator film CINSand the upper electrode EU each formed on the upper surface of the lowerelectrode EL inside each of the capacitor-forming trenches CGV areextended outside the capacitor-forming trench CGV to cover the uppersurface (main surface) of the interlayer dielectric INS3. When viewed inplan, the upper electrode EU is completely superimposed onto thecapacitive insulator film CINS so that these members have plane-shapesequal to each other. Each of the lower electrodes EL is formed into asmall thickness along/on the bottom surface and the side surface (sidewall) of one of the capacitor-forming trenches CGV, and the capacitiveinsulator film CINS and the upper electrode EU are put into thecapacitor-forming trench CGV. In other words, the bottom surface and theside surface of each of the capacitor-forming trenches CGV are used toform the capacitive insulator film CINS and the upper electrode EUalong/over the upper surface of each of the lower electrodes EL. Thus, asmall flat area is used to form the capacitive elements CON with a highcapacitance. The capacitive insulator film CINS may be a zirconium oxide(ZrO₂) film, a hafnium oxide (HfO₂) film, or a tantalum oxide (Ta₂O₅)film. The capacitive insulator film CINS may be a film in which titanium(Ti), aluminum (Al), yttrium (Y) or a lanthanoid is added to a zirconiumoxide (ZrO₂) film, a hafnium oxide (HfO₂) film, or a tantalum oxide(Ta₂O₅) film. The capacitive insulator film CINS is formed into athickness of 4 to 13 nm by an ALD method or a CVD method.

The upper electrode EU has a structure of three metal films, any one ofwhich does not exclude a metal-element-containing film. This structureis a laminated structure in which from thecapacitive-insulator-film-CINS-side thereof a first upper electrode EU1,a second upper electrode EU2 and a third upper electrode EU3 arelaminated in turn. About each of the first, the second and the thirdupper electrodes EU1, EU2 and EU3, the surface thereof that is near tothe capacitive insulator film CINS is called the lower surface thereof;and the surface thereof that is far therefrom, the upper surfacethereof.

The first upper electrode EU1 may be a film including a metal ormetal-element-containing material, such as titanium nitride (TiN),titanium (Ti), platinum (Pt), indium (Ir) or ruthenium (Ru). This filmcan be formed into a thickness of 10 to 50 nm by an MOCVD method or anALD method. Over the respective bottom surfaces and side surfaces of thecapacitor-forming trenches CGV, the first upper electrode EU1 contactsthe capacitive insulator film CINS; thus, when the first upper electrodeEU1 is formed by an MOCVD method, which less gives a plasma damage ontothe capacitive insulator film CINS than an ALD method, a leakage currentin the capacitive elements CON can be decreased. When the first upperelectrode EU1 is rendered a titanium nitride (TiN) film formed by theMOCVD method, the film density thereof is from 2.5 to 3.5 g/cm³.

The second upper electrode EU2 may be a film including a metal ormetal-element-containing material, such as titanium nitride (TiN),titanium (Ti), platinum (Pt), indium (Ir) or ruthenium (Ru). This filmcan be formed into a thickness of 1.5 to 8 nm by an ALD method, an MOCVDmethod or a PVD method. The second upper electrode EU2 is formed tocover the front surface of the first upper electrode EU1. Over therespective bottom surfaces and side surfaces of the capacitor-formingtrenches CGV, the second upper electrode EU2 contacts the first upperelectrode EU1. The second upper electrode EU2 is a bather film forpreventing or decreasing the diffusion of an impurity, such as fluorine(F), contained in the third upper electrode EU3, which will be detailedbelow, into the first upper electrode EU1 and the capacitive insulatorfilm CINS. The second upper electrode EU2 is made thin as far as thiselectrode attains a function as the bather film. By making the secondupper electrode EU2 thinner than, for example, the first upper electrodeEU1, the proportion of the film thickness of the third upper electrodeEU3 in that of the upper electrode EU can be made high.

The third upper electrode EU3 is a tungsten (W) film formed by a CVDmethod. The third upper electrode EU3 is formed to decrease theresistance of the upper electrode EU; thus, it is effective that thethird upper electrode EU3 is a metal film smaller in electricresistivity than the first and second upper electrodes EU1 and EU2. Forreference, the electric resistance of tungsten (W) is 52.8 nΩ·m and thatof titanium nitride (TiN) is 217 nΩ·m at room temperature (20° C.). Overthe respective bottom surfaces and side surfaces of thecapacitor-forming trenches CGV, the third upper electrode EU3 contactsthe second upper electrode EU2 to prevent the following: the electricpotential of the upper electrode EU at the bottom of thecapacitor-forming trenches CGV fluctuates against an electric potentialsupplied to the upper electrode EU. By forming the third upper electrodeEU3 to have a sufficient thickness, the capacitor-forming trenches CGVare completely embedded therewith so that the third upper electrode EU3has a flat upper surface. In other words, regions of the interlayerdielectric INS3 where the capacitor-forming trenches CGV are made, andother regions thereof have a flat upper surface. The film thickness ofthe third upper electrode EU3 over the interlayer dielectric INS3 isfrom 20 to 100 nm. However, since tungsten films are formed by a CVDmethod using WF₆ gas, the third upper electrode EU3 (i.e., a tungstenfilm) contains fluorine (F) as an impurity.

The third upper electrode EU3 is not necessarily limited to any tungsten(W) film. It is sufficient for the third upper electrode EU3 to be afilm which is lower in electric resistivity than the first and secondupper electrodes EU1 and EU2 and may contain an impurity.

In order to cover the upper electrode EU, an interlayer dielectric INS4is formed on the upper electrode EU. In the logic circuit region LGC,the capacitive insulator film CINS and the upper electrode EU on theinterlayer dielectric INS3 are removed, so that the interlayerdielectric INS4 is formed on the interlayer dielectric INS3. In the DRAMregion DR, a contact hole CH3 is made in the interlayer dielectric INS4to penetrate the interlayer dielectric INS4. In the logic circuit regionLGC, a contact hole CH3 is made in a laminated structure of the stopperfilm STP1, and the interlayer dielectrics INS3 and INS4. Inside thecontact hole CH3 in each of the DRAM region DR and the logic circuitregion LGC, a plug electrode PLG3 which is made of a conductor film isformed. The interlayer dielectric INS4 is an insulator film such as asilicon oxide film. The plug electrode PLG3 is formed to have alaminated structure of the following two: a thin bather conductor film(such as a titanium nitride (TiN) film, a titanium (Ti) film or alaminated film of the two) functioning as a bather metal; and a mainconductor film (such as a tungsten film) that is larger in filmthickness than the barrier conductor film. In the DRAM region DR, theplug electrode PLG3 contacts the third upper electrode EU3 of thecapacitive elements CON to be electrically coupled thereto. In the logiccircuit region LGC, the plug electrode PLG3 contacts the plug electrodePLG2 and the interconnection M1 to be electrically coupled thereto.

In order to cover the plug electrodes PLG3, an interlayer dielectricINS5 is formed on the interlayer dielectric INS4. The interlayerdielectric INS5 is an insulator film, for example, a low-k film such asa silicon oxide film or a SiCOH film. Plural interconnection trenchesCH4 are made in the interlayer dielectric INS5 to penetrate theinterlayer dielectric INS5. Inside the interconnection trenches CH4, aninterconnection M2 is formed. The interconnection M2 may be a copperinterconnection, and is formed to have a laminated structure of thefollowing two: a thin bather conductor film (such as a tantalum (Ta)film, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or alaminated film of two or more of these films) functioning as a barriermetal; and a main conductor film (such as a copper (Cu) film) that islarger in film thickness than the barrier conductor film. Theinterconnection M2 contacts the respective upper surfaces (mainsurfaces) of the plug electrodes PLG3 to be electrically coupledthereto.

Hereinafter, a further description will be made about the second andthird upper electrodes EU2 and EU3, and a description will also be madeabout advantageous effects of the present embodiment.

In the DRAM region DR, for example, a determined supply electricpotential Vcc or Gnd is supplied through the interconnection M2 and theplug electrode PLG3 to the upper electrode EU of the capacitive elementsCON. In other words, the interconnection M2 and the plug electrode PLG3in the DRAM region DR shown in FIG. 2 are electric-power supply meansfor the upper electrode EU of the capacitive elements CON. Theelectric-power supply means are arranged collectively, for example, at aperipheral portion of the DRAM cell array, so that, out of the entireDRAM cells, ones arranged at a central portion of the DRAM cell arrayare present at positions far from the electric-power supply means. Whenthe electric resistance of the upper electrode EU is high, the electricpotential of the upper electrode EU of the DRAM cells arranged at thecentral portion of the DRAM cell array fluctuates (deviates) from thesupply electric potential to cause a problem that the quantity ofcharges accumulated in the capacitive elements CON is decreased. Inorder to solve this problem, the third upper electrode EU3, which is ametal film smaller in electric resistivity than the first and secondupper electrodes EU1 and EU2, is laid to decrease the electricresistance of the upper electrode EU. In conclusion, even in thecapacitive elements CON of the DRAM cells positioned at the centralportion of the DRAM cell array, the electric potential of their upperelectrode EU can be made substantially equal to the supply electricpotential, so that the present embodiment has an advantageous effectthat even in the DRAM cells at the central portion, sufficient electriccharges can be accumulated into their capacitive elements CON.

When attention is paid to each of the capacitive elements CON, thepresent embodiment has an advantageous effect that a fluctuation in theelectric potential of the upper electrode EU along/over the bottomsurface of each of the capacitor-forming trenches CGV can be decreasedby forming the third upper electrode EU3 deeply inside thecapacitor-forming trench CGV. It is therefore effective for decreasingthe electric potential fluctuation of the upper electrode EU that thethird upper electrode EU3 contacts the second upper electrode EU2 at thebottom of the capacitor-forming trench CGV.

As described above, the second upper electrode EU2 is a barrier film forpreventing the diffusion of the impurity, such as fluorine (F),contained in the third upper electrode EU3 into the first upperelectrode EU1 or the capacitive insulator film CINS. Accordingly, thepresent embodiment has an advantageous effect that a leakage in thecapacitive insulator film CINS can be prevented or decreased byinterposing the second upper electrode EU2, which is a bather film,between the third upper electrode EU3, and the first upper electrode EU1or the capacitive insulator film CINS.

Furthermore, a more effective result is obtained by making the secondupper electrode EU2 higher (or larger) in film density than the firstupper electrode EU1. The use of a metal film or metal-element-containinglayer high in film density as the second upper electrode EU2 makes itpossible to improve the advantageous effect of preventing or decreasingthe impurity diffusion, thereby forming the second upper electrode EU2thinly. The matter that the second upper electrode EU2 can be made thinmakes it possible to form the third upper electrode EU3 deeply insidethe first and second upper electrodes EU1 and EU2 positioned inside eachof the capacitor-forming trenches CGV to decrease a fluctuation in theelectric potential of the upper electrode EU at the bottom of thecapacitor-forming trench CGV also.

It is also important that the second upper electrode EU2 does not haveany hole (opening) or any other that is to be a path through whichfluorine (F) diffuses. Since the second upper electrode EU2 is made of ametal film or a metal-element-containing film, it is unnecessary to makeany opening (connecting hole or bore) through which the first and thirdupper electrodes EU1 and EU2 are electrically coupled to each other. Inthe region of the DRAM cell array, the upper electrode EU2 is a filmwhich covers the first upper electrode EU1 completely and has noopening, and further covers the front surface (upper surface) of thefirst upper electrode EU1 completely in each of the capacitor-formingtrenches CGV also.

For reference, the capacitive insulator film CINS, and the first, thesecond and the third upper electrodes EU1, EU2 and EU3 have plane-shapesequal to each other in design. This matter means that a single mask isused to work (pattern) the third, the second and the first electrodesEU3, EU2 and EU1, and the capacitive insulator film CINS successively.In other words, plane-shapes having a difference in finish dimensionthat follows the working, such as etching, are included in the categorydenoted by the wording “plane-shapes equal to each other in design”. Itis not essential that the second upper electrode EU2 is equal inplane-shape to the first upper electrode EU1. It is important that thesecond upper electrode EU2 completely covers the front surface (uppersurface) of the first upper electrode EU1 when viewed in plan. It istherefore allowable that the second upper electrode EU2 is larger inplane-size than the first upper electrode EU1. The second upperelectrode EU2 completely covers the front surface of the first upperelectrode EU1; thus, it is possible to prevent the impurity diffusionfrom the third upper electrode EU3 to the first upper electrode EU1 orthe capacitive insulator film CINS. It is therefore possible to decreasea leakage in the capacitive insulator film CINS.

The following will describe a method for producing the semiconductorintegrated circuit device of the present embodiment.

FIGS. 3 to 10 are each a sectional view illustrating a main portion of aworkpiece of the semiconductor integrated circuit device of the presentembodiment when this device is produced. FIG. 3 is a view referred tofor describing the step of preparing a semiconductor substrate SB inwhich selective MISFETs (TR1) and a logic MISFET (TR2) are formed, andthe step of forming an interlayer dielectric INS1. The selective MISFETs(TR1) are formed in a DRAM region DR of the semiconductor substrate SB,and the logic MISFET (TR2) is formed in a logic circuit region LGCthereof. In order to cover the selective MISFETs (TR1) and the logicMISFET (TR2), the interlayer dielectric INS1 is formed on a main surfaceof the semiconductor substrate SB. Specifically, a silicon oxide film,which is to be the interlayer dielectric INS1, is formed onto the mainsurface of the semiconductor substrate SB by, for example, aplasma-enhanced chemical vapor deposition (plasma CVD). The filmthickness of the silicon oxide film is made larger than a film thickness(for example, about 350 nm) permitting a space between gate electrodesG1 adjacent to each other to be completely embedded with the siliconoxide film. Next, the interlayer dielectric INS1 is subjected tochemical mechanical polishing (CMP) treatment to flatten the frontsurface of the interlayer dielectric INS1, thereby forming theinterlayer dielectric INS1 to have a flat main surface (upper surface).

FIG. 4 is a view referred to for describing the step of making contactholes CH1 in the interlayer dielectric INS1, the step of forming plugelectrodes into the contact holes CH1, and the step of forming aninterlayer dielectric INK thereon. A resist film PR1 (not illustrated)that is an insulator film is formed on the interlayer dielectric INS1.The resist film PR1 has openings corresponding to the contact holes CH1.The resist film PR1 is used as a mask to subject the interlayerdielectric INS1 to dry etching, thereby making the contact holes CH1 inthe interlayer dielectric INS1.

Next, a bather conductor film and a main conductor film are successivelyformed (or deposited) onto the interlayer dielectric INS1. The formationof the barrier conductor film and the main conductor film is performedto give a film thickness permitting the contact holes CH1 to becompletely embedded with these films. Thereafter, the main conductorfilm is subjected to CMP treatment to remove the main conductor film andthe barrier conductor film on the interlayer dielectric INS1. By the CMPtreatment, the main conductor film and the bather conductor film arecaused to remain only inside the contact holes CH1, thereby forming asource plug electrode PLGS, drain plug electrodes PLGD and plugelectrodes PLG1, each of these electrodes being made of the laminatedfilm of the barrier conductor film and the main conductor film.

Next, in order to cover the source plug electrode PLGS, the drain plugelectrodes PLGD and the plug electrodes PLG1, an interlayer dielectricINK is formed on the interlayer dielectric INS1 by a PCVD method.

FIG. 5 is a view referred to for describing the step of formingcapacitive plug electrodes PLGC, a bit line BL, a plug electrode PLG2,and an interconnection M1, and the step of forming a stopper film STP1.Onto the interlayer dielectric INS2, a resist film PR2 (not illustrated)is formed which has openings corresponding to the capacitive plugelectrodes PLGC, the bit line BL, the plug electrode PLG2 and theinterconnection M1. Next, the resist film PR2 is used as a mask tosubject the interlayer dielectric INK to dry etching, thereby makingcontact holes CH2 b and interconnection trenches CH2 a in the DRAMregion DR and the logic circuit region LGC.

Next, a bather conductor film and a main conductor film are successivelyformed (or deposited) on the interlayer dielectric INS2. The formationof the barrier conductor film and the main conductor film is performedto give a film thickness permitting the interconnection trenches CH2 aand the contact holes CH2 b to be completely embedded with these films.Thereafter, the main conductor film and the barrier conductor film aresubjected to CMP treatment to remove the main conductor film and thebarrier conductor film on the interlayer dielectric INS2. By the CMPtreatment, the main conductor film and the barrier conductor film arecaused to remain only inside the interconnection trenches CH2 a and thecontact holes CH2 b, thereby forming capacitive plug electrodes PLGC, aplug electrode PLG2, a bit line and an interconnection M1, each of thesemembers being made of the laminated film of the bather conductor filmand the main conductor film.

Next, in order to cover the capacitive plug electrodes PLGC, the plugelectrode PLG2, the bit line BL and the interconnection M1, a stopperlayer STP1 is formed (or deposited) on the interlayer dielectric INS2 bya PCVD method.

FIG. 6 is a view referred to for describing the step of makingcapacitive contact holes CCH in the stopper layer STP1. Onto the stopperfilm STP1, a resist film PR3 (not illustrated) is formed which is aninsulator film having openings corresponding to the capacitive contactholes CCH. The resist film PR3 is used as a mask to subject the stopperfilm STP1 to dry etching, thereby making the capacitive contact holesCCH. The capacitive contact holes CCH are made on the capacitive plugelectrodes PLGC to make the respective tops (upper surfaces) of thecapacitive plug electrodes PLGC naked.

FIG. 7 is a view referred to for describing the step of forming aninterlayer dielectric INS3 having capacitor-forming trenches CGV. Theinterlayer dielectric INS3, which is an insulator film, is formed (ordeposited) onto the stopper film STP1 by a plasma CVD method. Next, ontothe interlayer dielectric INS3, a resist film PR4 (not illustrated) isformed which is an insulator film having openings corresponding to apattern of the capacitor-forming trenches CGV. The resist film PR4 isused as a mask to subject the interlayer dielectric INS3 to dry etching,thereby making the capacitor-forming trenches CGV. In the DRAM regionDR, the capacitor-forming trenches CGV are each formed on any one of thecapacitive plug electrodes PLGC. The stopper film STP1, the capacitivecontact holes CCH and the capacitive plug electrodes PLGC are exposed tothe bottom of the capacitor-forming trenches CGV.

FIG. 8 is a view referred to for describing the step of forming lowerelectrodes EL. Each of the lower electrodes EL, which is made of aconductor film, is formed into a small and even thickness, along/on theside wall and the bottom surface of any one of the capacitor-formingtrenches CGV, in such a manner that the capacitor-forming trench CGV isnot embedded with the lower electrode EL. The lower electrode EL is madeof a titanium nitride (TiN) formed by an MOCVD method. The titaniumnitride (TiN) film can be formed into a desired thickness, for example,by repeating, plural times, a cycle of depositingtetrakisdimethylaminotitanium (TDMAT) into the capacitor-forming trenchCGV and then subjecting the resultant TDMAT layer to plasma treatmentwith a mixed gas of hydrogen and nitrogen for 5 to 40 seconds. The lowerelectrode EL is formed also in any one of the capacitive contact holesCCH to contact the upper surface of one of the capacitive plugelectrodes PLGC. The lower electrode EL is separated from the otherlower electrode EL, which is formed in the capacitor-forming trench CGVadjacent to the former lower electrode EL. An end EDG of the lowerelectrode EL, i.e., each of the lower electrodes EL, is not extended tothe upper surface (main surface) of the interlayer dielectric INS3 to beterminated at a position below the upper surface (main surface) of theinterlayer dielectric INS3.

After the formation of the lower electrode EL, the workpiece is annealedto crystalize the titanium nitride film. The annealing is performed inan atmosphere of, for example, a nitrogen (N₂) at a temperature rangefrom 340 to 450° C. Instead of the nitrogen atmosphere, an atmosphereof, for example, argon (Ar) or helium (the) is usable.

FIG. 9 is a view referred to for describing the step of forming acapacitive insulator film CINS, and an upper electrode EU. Thecapacitive insulator film CINS, which is a zirconium oxide (ZrO₂) film,is formed (or deposited) along/on or over the upper surface of the lowerelectrode EL by an ALD method. For example, the following cycle is used:a cycle including a first step of using tetraethylmethylaminozirconium(TEMAZ) containing zirconium (Zr) as a raw material gas to depositzirconium (Zr) into a single-atom layer on the lower electrode EL, and asecond step of supplying an oxidizer such as ozone (O₃) onto the frontsurface of the zirconium (Zr) layer to form a zirconium oxide (ZrO₂)film. This cycle is repeated plural times to form the capacitiveinsulator film CINS, which is the zirconium oxide (ZrO₂) film, into adesired film thickness.

After the formation of the capacitive insulator film CINS, the workpieceis annealed. For example, the workpiece is annealed in an atmosphere of,for example, nitrogen (N₂), argon (Ar), or helium (He) at a temperaturehigher than the temperature for forming the capacitive insulator filmCINS. This annealing makes it possible to improve the capacitiveinsulator film CINS in film quality and dielectric constant.

Next, a first upper electrode EU1 is formed on the front surface of thecapacitive insulator film CINS. The first upper electrode EU1 is made ofa titanium nitride (TiN) film formed by an MOCVD method. For example,the following cycle is used: a cycle including a first step ofdepositing tetrakisdimethylaminotitanium (TDMAT) on the upper surface ofthe capacitive insulator film CINS in FIG. 9, and a second step ofsubjecting the resultant TDMAT layer to plasma treatment with a mixedgas of hydrogen and nitrogen for 5 to 40 seconds. This cycle isperformed once, or repeated plural times to form the titanium nitride(TiN) film into a desired film thickness. According to the formation ofthe first upper electrode EU1 by the MOCVD method, a plasma damage ontothe capacitive insulator film CINS can be made smaller than according tothat by an ALD method or PVD method. Thus, a leakage in the capacitiveinsulator film CINS can be decreased.

Next, a second upper electrode EU2 is formed on the front surface of thefirst upper electrode EU1. The second upper electrode EU2 may be made ofa titanium nitride (TiN) film formed by an ALD method. The titaniumnitride (TiN) film can be formed into a desired thickness, for example,by repeating the following cycle 7 to 33 times: a cycle of exposing thesemiconductor substrate SB in FIG. 9 over which the first upperelectrode EU1 has been formed but no more member has been formed totetrakisdimethylaminotitanium (TDMAT) as a raw material gas to form asingle layer of TDMAT, and then subjecting this single TDMAT layer toplasma treatment with nitrogen gas for 2 to 10 seconds.

By making the second upper electrode EU2 larger in film density than thefirst upper electrode EU1, a bather layer resisting the diffusion ofimpurities from a third upper electrode EU3, which will be describedjust below, can be formed as a thin film. When the second upperelectrode EU2 is, for example, a titanium nitride (TiN) film by an ALDmethod, this film can be formed as a dense film by elongating the periodfor the plasma treatment with the nitride gas. In accordance with therepeated number of the cycle, the film thickness thereof can becontrolled.

Next, the third upper electrode EU3 referred to the above is formed ontothe front surface of the second upper electrode EU2. The third upperelectrode EU3 is a tungsten (W) film formed by a CVD method using WF₆gas. The third upper electrode EU3 is formed on the upper surface of thesecond upper electrode EU2 formed along/over the bottom surface and theside wall of each of the capacitor-forming trenches CGV. The third upperelectrode EU3 is formed into a sufficiently large thickness in such amanner that the capacitor-forming trench CGV is completely embedded withthe third upper electrode EU3. Thereafter, the front surface of thetungsten (W) film is subjected to CMP polishing to complete the thirdupper electrode EU3 in the DRAM cell array as illustrated in FIG. 9, soas to have a substantially flat surface (upper surface). Next, a resistfilm PR5 (not illustrated) is used to work (pattern) the third upperelectrode EU3, the second upper electrode EU2, the first upper electrodeEU1, and the capacitive insulator film CINS in turn, thereby forming, inthe DRAM region DR, the third upper electrode EU3, the second upperelectrode EU2, the first upper electrode EU1, and the capacitiveinsulator film CINS, which have, respectively, plane-shapes equal toeach other in design. In other words, this working (patterning) attainsthe removal of the third upper electrode EU3, the second upper electrodeEU2, the first upper electrode EU1, and the capacitive insulator filmCINS in the logic circuit region LGC.

The capacitive insulator film CINS and the upper electrode EU are eacharranged commonly or singly for the plural lower electrodes EL.Specifically, in the DRAM region DR, the capacitive insulator film CINSand the upper electrode EU are continuously extended from the respectiveinsides of the capacitor-forming trenches CGV adjacent to each other tothe interlayer dielectric INS3 between these capacitor-forming trenchesCGV.

FIG. 10 is a view referred to for describing the step of forming aninterlayer dielectric INS4 and plug electrodes PLG3. In order to coverthe upper electrode EU in the DRAM region DR and the interlayerdielectric INS3 in the logic circuit region LGC, the interlayerdielectric 4, which is an insulator film, is formed by a CVD method. Theinterlayer dielectric INS4 is, for example, a silicon oxide film formedby a plasma CVD method. In the step of forming this interlayerdielectric INS4, a thermal load of 400° C. or higher is applied to thesemiconductor substrate SB. After the interlayer dielectric INS4 isdeposited by the plasma CVD method, CMP treatment is applied to theinterlayer dielectric INS4 in the DRAM region DR and the logic circuitregion LGC to flatten the front surface of the interlayer dielectricINS4.

Next, in the DRAM region DR, one of the plug electrode PLG3 is locatedto penetrate the interlayer dielectric INS4, and thus the plug electrodePLG3 is brought into contact with the upper electrode EU so that the twoare electrically coupled to each other. In the logic circuit region LGC,the other plug electrode PLG3 is located to penetrate the interlayerdielectric INS4, the interlayer dielectric INS3 and the stopper filmSTP1, and thus the plug electrode PLG3 is brought into contact with theplug electrode PLG2 and the interconnection M1, so as to be electricallycoupled to the plug electrode PLG2 and the interconnection M1. In theDRAM region DR and the logic circuit region LGC, contact holes CH3 ineach of which one of the plug electrodes PLG3 is formed are different indepth from each other; however, the contact holes CH3 are simultaneouslymade, using, for example, a dry etching method. When the contact holesCH3 are made, the upper electrode EU functions, in the DRAM region DR,as an etching stopper for stopping the etching of the interlayerdielectric INS4 and the interlayer dielectric INS3; and the stopper filmSTP1 does, in the Logic circuit region LGC, as the same.

Next, in order to cover the plug electrodes PLG3, an interlayerdielectric INS5, which is an insulator film such as a silicon oxidefilm, is formed by, for example, a plasma CVD method. Also in this stepof forming the interlayer dielectric INS5, a thermal load of 400° C. orhigher is applied to the semiconductor substrate SB. Thereafter,interconnection trenches CH4 a are made in the interlayer dielectricINS5, and then an interconnection M2 made of a copper interconnection isformed inside the interconnection trenches CH4 a to complete thestructure illustrated in FIG. 2. In the DRAM region DR, theinterconnection M2 is electrically coupled to the upper electrode EU ofthe capacitive elements CON through the plug electrode PLG3, so thatthrough the interconnection M2, a predetermined voltage is supplied tothe upper electrode EU. In the logic circuit region LGC, theinterconnection M2 is electrically coupled to the source region SR2 ordrain region DR2 of the logic MISFET (TR2), so that through theinterconnection M2, a predetermined electric potential or signal issupplied to the source region SR2 or the drain region DR2 of the logicMISFET (TR2).

In the present embodiment, the step of forming the secondinterconnection layer and the steps previous thereto have beendescribed. Actually, however, steps of forming interconnections that areplural layers will be performed. In each of the steps, a thermal loadgenerated at the time of the formation of an interlayer dielectrictherefor will be applied to the semiconductor substrate SB.

When impurities, such as fluorine (F), contained in the tungsten (W)film, of which the third upper electrode EU3 is made, are diffused intothe capacitive insulator film CINS by the thermal load in any one of theinterlayer-dielectric-forming steps after the formation of thecapacitive elements CON, a leakage is generated in the capacitiveinsulator film CINS. In the present embodiment, between the third upperelectrode containing the impurities, and the first upper electrode EU1or the capacitive insulator film CINS, the second upper electrode EU2,which functions as a barrier film against the diffusion of theimpurities, is interposed. Thus, even when the thermal load in theinterconnection-forming step is applied to the capacitive elements CON,a leakage can be prevented in the capacitive insulator film CINS.

FIG. 11 is a graph showing a relationship between the film density ofthe bather film and the film thickness thereof. FIG. 11 specificallyshows the following: in the case of rendering the bather film a titaniumnitride (TiN) film, a relationship between the film density (X) of thetitanium nitride (TiN) film and the film thickness (Y) thereof that arenecessary for reducing the concentration of fluorine (F) passing throughthe barrier film by one digit. The relationship between the two isrepresented by the following expression:

Y=16.1^(e-0.36X)  (1)

It is therefore effective to use, as the barrier film, a titaniumnitride (TiN) film satisfying the following expression:

“Y0”≧16.1^(e-0.36“X0”)  (2)

wherein X0 represents a predetermined film density of the film; Y0, thefilm thickness thereof that corresponds to the predetermined filmdensity. When the fluorine (F) concentration can be reduced by onedigit, the capacitive elements CON of the MIM structure can besufficiently prevented from undergoing a leakage deterioration.

FIG. 12 is a graph showing a relationship between the leakage current ofeach of two species of capacitive elements CON each having an MIMstructure and a cumulative probability distribution of samples of thespecies. A comparison was made about leakage current between one of thetwo species, i.e., a case of making the upper electrode EU into abilayered structure of the first upper electrode EU1 (titanium nitridefilm having a film thickness of 30 nm) and the third upper electrodeEU3, and the other species, i.e., a case of making the upper electrodeEU into a trilayered structure of the first upper electrode EU1(titanium nitride film having a film thickness of 30 nm), the secondupper electrode EU2 (bather film) and the third upper electrode EU3. Asid evident from the results, in the case of laying no barrier film, theleakage current is increased by the thermal load. However, by laying thebarrier film, the leakage current based on the thermal load can bedecreased by about one digit. The used barrier film was a titaniumnitride (TiN) film having a film density of 4.35 g/cm³ and a filmthickness of about 3 nm. About the thermal load, an annealing wasconducted at 420° C. for 50 minutes on the supposition that aninterconnection-forming step (as described above) is simulated.

FIG. 13 is a view showing a concentration distribution of fluorine inthe depth direction of each of two samples of the first upper electrodeEU1. One (A) of the two samples was prepared by laying, for example, atungsten (W) film (third upper electrode EU3) containing fluorine (F)onto, for example, a titanium nitride (TiN) film (first upper electrodeEU1). The other sample (B) was prepared by laying, for example, atungsten (W) film (third upper electrode EU3) containing fluorine (F)onto a titanium nitride (TiN) film (first upper electrode EU1) tointerpose, therebetween, a bather film (second upper electrode EU2)which was a titanium nitride (TiN) film. Next, the samples (A) and (B)were annealed, for example, at 420° C. for 50 minutes. About each of theannealed samples (A) and (B), a distribution of the fluorine (F)concentration was measured from the front surface of the tungsten (W)film. The results are shown in FIG. 13. It is understood that by layingthe barrier film, the concentration of fluorine (F) diffusing into thefirst upper electrode EU1 can be decreased by about one digit. The usedbather film was a titanium nitride (TiN) film having a film density of4.35 g/cm³ and a film thickness of about 3 nm.

FIG. 14 is a graph showing a relationship between the depth (or movingdistance) of fluorine diffusing into each of second electrodes EU2(bather film) species and the concentration of fluorine therein. Thedata were obtained by measurements according to backside secondary ionmass spectrometry (SIMS). FIG. 14 specifically shows a relationshipbetween the depth and concentration of fluorine (F) about the speciesthat are four bather film species different from each other in filmdensity. As is evident from this graph, as the density of the film islarger, the film can block the invasion of fluorine (F) in the range ofa shorter distance. The used bather film was a titanium nitride (TiN)film having a film thickness of about 3 nm.

Herein, the description has been made, using, as the bather film, a filmin which the concentration of fluorine (F) passing through the batherfilm was reduced by one digit. It is however unessential to reduce thefluorine (F) concentration by one digit.

As has been described with reference to FIG. 10, the front surface ofthe interlayer dielectric INS4 has been subjected to CMP treatment. Whenattention is paid to the DRAM region DR and the logic circuit regionLGC, the respective interlayer-dielectric-INS3-front surfaces in the tworegions are substantially equal in height to each other. When the stepof forming the capacitive elements CON is next finished, only the DRAMregion DR has the capacitive insulator film CINS and the upper electrodeEU of the capacitive elements CON. Consequently, the height of the frontsurface of the interlayer dielectric INS4 subjected to the CMP treatmentunfavorably becomes higher in the DRAM region DR than in the logiccircuit region LGC, which is not illustrated. In other words, betweenthe DRAM region DR and the logic circuit region LGC, a global step(level difference) is unfavorably generated to cause a problem oflowering the working precision in the step of making the contact holesCH3, in which the plug electrodes PLG3 are to be made, the step offorming the interconnection M2, and other steps. This problem is alsocaused at the time of working into plural interconnections to be formedover the interconnection M2.

The present embodiment makes it possible to cause the second upperelectrode EU2 to have a function as a bather film to decrease the filmthickness of the upper electrode EU. Thus, the embodiment has anadvantageous effect that the global step can be decreased and theworking precision can be improved.

Second Embodiment

Second embodiment corresponds to a modified example of the Firstembodiment.

In the present embodiment, the second upper electrode EU2 of the Firstembodiment in FIG. 9 is formed by a remote plasma nitriding method.Specifically, in the same way as in the First embodiment, the firstupper electrode EU1 in FIG. 9, which is a nitride titanium (TiN) film,is formed by, for example, an MOCVD method. Thereafter, an already knownremote plasma nitriding method is used to nitride the front surface ofthe titanium nitride film, which is the first upper electrode EU1, toform a second upper electrode EU2. The titanium nitride film of whichthe second upper electrode EU2 is made is larger in nitrogenconcentration than the titanium nitride film of which the first upperelectrode EU1 is made. Moreover, the titanium nitride film of which thesecond upper electrode EU2 is made is larger in film density than thetitanium nitride film of which the first upper electrode EU1 is made.

The Second embodiment is identical with the First embodiment except thismethod for forming the second upper electrode EU2.

Accordingly, the second upper electrode EU2, which is higher in filmdensity than the first upper electrode EU1, is interposed between thethird upper electrode EU3, and the first upper electrode EU1 or thecapacitive insulator film CINS, thereby producing an advantageous effectthat the present embodiment makes it possible to prevent a leakage inthe capacitive insulator film CINS which is caused by the diffusion ofimpurities from the third upper electrode EU3.

The above has specifically described an invention made by the inventorsby way of the embodiments thereof. However, the present invention is notlimited to the embodiments. Thus, of course, the embodiments can each bevariously modified as far as the modified embodiment does not departfrom the subject matter thereof.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising a plurality of DRAM cells each comprising a selective MISFETand a capacitive element that are coupled in series to each other, thedevice comprising: a semiconductor substrate, a first insulator filmformed over a main surface of the semiconductor substrate, and having acapacitor-forming trench comprising a side wall and a bottom surface, alower electrode formed along/over the side wall and the bottom surfacecomprised in the capacitor-forming trench, a capacitive insulator filmformed over the lower electrode to cover the lower electrode, a firstupper electrode formed over the capacitive insulator film to cover thecapacitive insulator film, a second upper electrode formed over thefirst upper electrode to cover the first upper electrode, a third upperelectrode formed over the second upper electrode to cover the secondupper electrode, and having a smaller electric resistivity than thefirst upper electrode and being allowable to contain an impurity,wherein the capacitive element comprises the lower electrode, thecapacitive insulator film, and an upper electrode comprising the firstupper electrode, the second upper electrode and the third upperelectrode, wherein the second upper electrode is a bather layer forpreventing the possible impurity contained in the third upper electrodefrom diffusing into the capacitive insulator film, and wherein thesecond upper electrode is smaller in film thickness than the first upperelectrode.
 2. The semiconductor integrated circuit device according toclaim 1, wherein the second upper electrode is larger in film densitythan the first upper electrode.
 3. The semiconductor integrated circuitdevice according to claim 1, wherein the second upper electrode is afilm having no opening.
 4. The semiconductor integrated circuit deviceaccording to claim 1, wherein the third upper electrode comprises atungsten film.
 5. The semiconductor integrated circuit device accordingto claim 4, wherein the third upper electrode is smaller in electricresistivity than the second upper electrode.
 6. The semiconductorintegrated circuit device according to claim 1, wherein inside thecapacitor-forming trench, along/over the side wall and the bottomsurface, the lower electrode, the capacitive insulator film, the firstupper electrode, the second upper electrode, and the third upperelectrode are arranged in this order.
 7. The semiconductor integratedcircuit device according to claim 1, wherein the second upper electrodecomprises a titanium nitride film having a predetermined density (X) anda predetermined film thickness (Y), and wherein the titanium nitridefilm satisfies the following relational expression:Y≧16.1^(e-036X).
 8. The semiconductor integrated circuit deviceaccording to claim 1, wherein the capacitive insulator film is oneselected from the group comprising of a zirconium oxide film, a hafniumoxide film, and a tantalum oxide film.
 9. The semiconductor integratedcircuit device according to claim 8, wherein the lower electrode is oneselected from the group comprising of a titanium nitride film, atitanium film, and a tungsten film.
 10. The semiconductor integratedcircuit device according to claim 8, wherein the first upper electrodecomprises at least one selected from the group comprising of titaniumnitride, titanium, platinum, iridium, and ruthenium.
 11. A semiconductorintegrated circuit device, comprising a plurality of DRAM cells eachcomprising a selective MISFET and a capacitive element that are coupledin series to each other, the device comprising: a semiconductorsubstrate, a first insulator film formed over a main surface of thesemiconductor substrate, and having a capacitor-forming trenchcomprising a side wall and a bottom surface, a lower electrode formedalong/over the side wall and the bottom surface comprised in thecapacitor-forming trench, a capacitive insulator film formed over thelower electrode to cover the lower electrode, a first upper electrodeformed over the capacitive insulator film to cover the capacitiveinsulator film, a second upper electrode formed over the first upperelectrode to cover the first upper electrode, a third upper electrodeformed over the second upper electrode to cover the second upperelectrode, and having a smaller electric resistivity than the firstupper electrode, the third upper electrode comprising a tungsten filmhaving fluorine impurities therein, wherein the capacitive elementcomprises the lower electrode, the capacitive insulator film, and anupper electrode comprising the first upper electrode, the second upperelectrode and the third upper electrode, wherein the second upperelectrode is formed of a material capable of serving as a bather layerto prevent fluorine impurities contained in the third upper electrodefrom diffusing into the capacitive insulator film; and wherein thesecond upper electrode is smaller in film thickness than the first upperelectrode.
 12. A method for producing a semiconductor integrated circuitdevice, comprising the steps of: (a) forming a first insulator filmhaving a capacitor-forming trench comprising a side wall and a bottomsurface over a main surface of a semiconductor substrate; (b) forming alower electrode along/over the side wall and the bottom surface of thecapacitor-forming trench; (c) forming a capacitive insulator film overthe lower electrode to cover the lower electrode; (d) forming a firstupper electrode over the capacitive insulator film to cover thecapacitive insulator film; (e) forming a second upper electrode over thefirst upper electrode to cover the first upper electrode; and (f)forming a third upper electrode that may contain an impurity over thesecond upper electrode to cover the second upper electrode; thesemiconductor integrated circuit device comprising a capacitive element,the capacitive element comprising the lower electrode, the capacitiveinsulator film, the first upper electrode, the second upper electrode,and the third upper electrode, the second upper electrode being abarrier film for preventing the possible impurity contained in the thirdupper electrode from diffusing into the capacitive insulator film; andwherein the second upper electrode is formed to be smaller in filmthickness than the first upper electrode.
 13. The method for producing asemiconductor integrated circuit device according to claim 12, whereinthe second upper electrode is larger in film density than the firstupper electrode.
 14. The method for producing a semiconductor integratedcircuit device according to claim 13, wherein the second upper electrodeis formed by one selected from the group comprising of an ALD method, anMOCVD method, and a PVD method.
 15. The method for producing asemiconductor integrated circuit device according to claim 13, whereinthe second upper electrode is formed by nitriding the front surface ofthe first upper electrode by a remote plasma nitriding method.
 16. Themethod for producing a semiconductor integrated circuit device accordingto claim 12, wherein the first upper electrode is formed by one selectedfrom the group comprising of an MOCVD method and an ALD method.
 17. Themethod for producing a semiconductor integrated circuit device accordingto claim 12, wherein the capacitive insulator film is formed by oneselected from the group comprising of an ALD method and a CVD method.18. The method for producing a semiconductor integrated circuit deviceaccording to claim 12, wherein the lower electrode is formed by oneselected from the group comprising of an MOCVD method and an ALD method.19. The method for producing a semiconductor integrated circuit deviceaccording to claim 12, wherein the step of forming the third upperelectrode comprises the steps of: (g1) depositing a tungsten film overthe second upper electrode to embed the capacitor-forming trenchcompletely therewith, and (g2) subjecting the front surface of thetungsten film to CMP treatment.
 20. The method for producing asemiconductor integrated circuit device according to claim 19, whereinthe tungsten film is formed by a CVD method using WF₆ gas.